0. Ref

https://digilent.com/reference/learn/programmable-logic/tutorials/pmod-ips/start

 

Getting Started with Digilent Pmod IPs - Digilent Reference

 

digilent.com

파일 다운로드, 압축 풀기

Viviado 프로젝트 생성

Project Manager -> Settings -> IPs -> Repository -> Library 디렉토리 추가

Open Block -> Pmod -> Connector 선택 후 더블 클릭하면 Pmod IP 선택 간능

 

*** USBUART는 없음!!!

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0. Ref

https://digilent.com/reference/pmod/pmodusbuart/start?redirect=1 

 

Pmod USBUART - Digilent Reference

 

digilent.com

Pmod Connector 연결하여 PL에서 사용가능

1. ZYBO Z7 Port

clock: K11 <- Ethernet Phy Clock 125MHz

Button SW[4] = {K18, P16, K19, Y16}

Slide SW[4] = {G15, P15, W13, T16}

LED[4] = {M14, M15, G14, G15}

 

Pmod Port

Pmod JA (XADC) Pmod JB (Hi-Speed) Pmod JC (Hi-Speed) Pmod JD (Hi-Speed) Pmod JE (Hi-Speed) Pmod JF (MIO)
JA1: N15 JB1: T20 JC1: V15 JD1: T14 JE1: V12 JF1: MIO-13
JA2: L14 JB2: U20 JC2: W15 JD2: T15 JE2: W16 JF2: MIO-10
JA3: K16 JB3: V20 JC3: T11 JD3: P14 JE3: J15 JF3: MIO-11
JA4: K14 JB4: W20 JC4: T10 JD4: R14 JE4: H15 JF4: MIO-12
JA7: N16 JB7: Y18 JC7: W14 JD7: U14 JE7: V13 JF7: MIO-0
JA8: L15 JB8: Y19 JC8: Y14 JD8: U15 JE8: U17 JF8: MIO-9
JA9: J16 JB9: W18 JC9: T12 JD9: V17 JE9: T17 JF9: MIO-14
JA10: J14 JB10: W19 JC10: U12 JD10: V18 JE10: Y17 JF10: MIO-15

 

2. Vivado 순서

Board 파일을 이용하여 프로젝트 생성

Verilog 코드 추가 -> Open Elaborated Designs -> Schematic -> Pin Assign -> Generate Bitstream

또는

IP Integrator -> Create Block Design -> Code Drag&Drop -> Create Port -> Generate Output Products

 -> Generate HDL Wrapper -> Elaborated Designs ...

 

clk_wiz: 외부 125MHz 에서 내부 50MHz clock 생성

util_vector_logic: Pull-Down 되어 있는 Button SW 입력을 "1" 로 뒤집어 active low Reset에 연결

sw0,1: UART mode 설정

je1,2 : JE Connector에 Pmod USB UART와 연결

xslice: 8bit 중 LED로 갈 4bit 만 연결

 

3. PC와 연결

Hardware Manager에서 PL programming

Pmod USBUART와 PC를 USB Cable로 연결

Teraterm으로 실행 (9600)

 

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0. Ref

https://rubber-tree.tistory.com/category/Digital%20Logic/Zybo%20z7%20%ED%94%84%EB%A1%9C%EC%A0%9D%ED%8A%B8

 

'Digital Logic/Zybo z7 프로젝트' 카테고리의 글 목록

디지털 회로 기반 지식으로 보는 반도체/IT 산업

rubber-tree.tistory.com

 

https://digilent.com/reference/programmable-logic/zybo-z7/start

 

Zybo Z7 - Digilent Reference

 

digilent.com

1. Vivaod에 Board 추가

다운로드 파일

https://github.com/Digilent/vivado-boards

 

GitHub - Digilent/vivado-boards

Contribute to Digilent/vivado-boards development by creating an account on GitHub.

github.com

Xilinx\Vivado\2021.1\data\boards\board_files 에 zybo-z20 디렉토리 복사

 

2. Pcam 5C Image Sensor 

Raspberry Pi 와 호환

https://digilent.com/reference/add-ons/pcam-5c/reference-manual

 

Pcam 5C Reference Manual - Digilent Reference

 

digilent.com

Header J1
Pin Signal Direction Description Pin Signal Direction Description
1 GND   Power Supply Ground 9 MIPI_CLK_P Out MIPI CSI-2 Clock Positive
2 LANE0_N Out MIPI CSI-2 Lane 0 Negative 10 GND   Power Supply Ground
3 LANE0_P Out MIPI CSI-2 Lane 0 Positive 11 PWUP In Power supply and sensor enable
4 GND   Power Supply Ground 12 N/C   Not Connected
5 LANE1_N Out MIPI CSI-2 Lane 1 Negative 13 SCL I/O Serial Camera Control Bus (SCCB) Clock
6 LANE1_P Out MIPI CSI-2 Lane 1 Positive 14 SDA I/O Serial Camera Control Bus (SCCB) Data
7 GND   Power Supply Ground 15 VCC3V3   Power Supply (3.3V) Input
8 MIPI_CLK_N Out MIPI CSI-2 Clock Negative        

 

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1. VMWare: CentOS 6

* hostname

** /etc/sysconfig/network

** HOSTNAME=tttt

* Xilinx License File

** hostname

** return port (2222)

* Firewall Open (firewall-config)

** 2100 port tcp

** 2222 port tcp (return)

* IP 확인

** 192.168.xxx.yyy

 

2. Windows10

* IP 확인

** 192.168.xxx.1

* 연결 확인

** ping 192.168.xxx.yyy

* Port 확인

** tcping 설치

** tcping 192.168.xxx.yyy 2100

** tcping 192.168.xxx.yyy 2222

www.elifulkerson.com/projects/tcping.php

 

tcping.exe - ping over a tcp connection

tcping.exe - ping over a tcp connection tcping.exe is a console application that operates similarly to 'ping', however it works over a tcp port. There are many different implementions of this floating around, written independently by different people. Ther

www.elifulkerson.com

www.xilinx.com/support/answers/69577.html

 

AR# 69577: 2017.1 Licensing - SDNet 2017.1 - ERROR: SDNet cannot obtain license

I use a floating license for SDNet 2017.1.1.  An SDNet floating license is located on the main floating license server.  I have correctly set the environment variable to point to this server, however the SDNet tool still displays the following:  cannot

www.xilinx.com

 

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alchitry.com/

 

Welcome to Alchitry

Alchitry

alchitry.com

www.amazon.com/Taidacent-Development-Spartan6-Compatible-Arduino/dp/B07P39F1V6

 

Taidacent FPGA Development Board with Spartan6 XC6SLX Compatible with Arduino

Taidacent FPGA Development Board with Spartan6 XC6SLX Compatible with Arduino

www.amazon.com

www.aditech.co.kr/product/product3?m=view&bbs_id=z3&p=1&search_category=&seq=32

 

에디테크

 

www.aditech.co.kr

alchitry.com/blogs/tutorials/hdmi-shield-basics

 

HDMI Shield Basics

This tutorial covers the basis of using the HDMI Shield. There are a few components bundled in the Mojo IDE that make encoding and decoding HDMI streams easier. This tutorial gives a basic example for each one.

alchitry.com

Xilinx IP

https://www.xilinx.com/products/intellectual-property/hdmi.html#overview

 

HDMI

The LogiCORE™ IP HDMI Reference Design implements HDMI digital video interface in Xilinx FPGAs.

www.xilinx.com

Intel FPGA IP

https://www.intel.com/content/www/us/en/products/details/fpga/intellectual-property/interface-protocols/hdmi.html

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0. Download

https://www.intel.com/content/www/us/en/programmable/downloads/download-center.html

 

Download Center for FPGAs

OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.  Intel and Quartus are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.

www.intel.com

1. Concept

Platform Designer (Qsys)

   = IPs + HPS + FPGA

 

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