205.02.02

https://onedrive.live.com/?authkey=%21AOgFjM4waJnTONY&id=B2CDC3A30980D5BD%21182971&cid=B2CDC3A30980D5BD

 

Microsoft OneDrive

 

onedrive.live.com

 


기본

  • +5V Must
  • Main Power: Type-C@JTAG
  • Boot Mode
    • UU(00): JTAG
    • DU(10): QSPI, from FLASH, OLED Demo, Heat!!!
    • DD(11): SD Card, petalinux
  • Petalinux
    • microSD, FAT32
    • 02 Routine Project > "LINUX part \01petalinux2018.3 run \compiled boot 
      file"
    • BOOT.BIN, image.ub
    • UART port
      • 115200, 8, none, 1, no flow control
    • root/root

잘 동작하는지 보기위해 QSPI모드로 하고 Power Meter가 달린 USB-C 케이블 연결-> 1.-W 

전력은 크지 않은데 보드 뒤면이 점점 따뜻해 진다.

방열판 필요한데...


문서에서 Vivado 2018.3 버전을 사용하라고 한다.

AMD 홈펭이지에 Vivado Lab Version은 라이센스 필요없다고 하고 파일크기도 1GB 미만이다.

https://account.amd.com/en/forms/downloads/xef-vivado.html?filename=Xilinx_Vivado_Lab_Win_2018.3_1207_2324.tar.gz

-> 이건 프로그래밍만 가능 ㅠㅠ


2025.02.03

최신 버전의 Unified Install로 2024.2 설치했다.

Zynq 7010, 7020은 라이센스 없이도 빌드가 잘된다.

다운받은 파일에서 02_Creat project under VIVADO.pdf 를 따라하면 된다.

직접 코딩하고 핀 매핑해도 되지만 파일에 있는 *.v, *.xdc 를 보면

C:\Work\FPGA\ZYNQ_MINI_ New\03 Sample Projects\7010\FPGA部分\fpga_01_pl_led_stream

module led_stream(
    output reg [3:0] led,  // LED4 to LED1, 1 on, 0 off
    input            clk,  // FPGA PL clock, 50 MHz
    input            rst_n // FPGA reset pin
);
 reg [31:0] cnt;
 reg [1:0]  led_on_number;
    //clock input 50000000
parameter CLOCK_FREQ  =50000000;
parameter COUNTER_MAX_CNT=CLOCK_FREQ/2-1;//change time 0.5s

    always @(posedge clk, negedge rst_n) begin
        if(!rst_n) begin
            cnt <= 32'd0;
            led_on_number <= 2'd0;
        end
        else begin
            cnt <= cnt + 1'b1;
            if(cnt == COUNTER_MAX_CNT) begin//¼ÆÊý0.5s
                cnt <= 32'd0;
                led_on_number <= led_on_number + 1'b1;
            end
        end
    end
    always @(led_on_number) begin
        case(led_on_number)
            0: led <= 4'b0001;
            1: led <= 4'b0010;
            2: led <= 4'b0100;
            3: led <= 4'b1000;
        endcase
    end
endmodule

 

set_property PACKAGE_PIN T12 [get_ports {led[3]}]
set_property PACKAGE_PIN U12 [get_ports {led[2]}]
set_property PACKAGE_PIN V12 [get_ports {led[1]}]
set_property PACKAGE_PIN W13 [get_ports {led[0]}]
set_property PACKAGE_PIN K17 [get_ports clk]
set_property PACKAGE_PIN M19 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]

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Eleparts Device Mart IC Bank Digi-Key Golden Gate
1 PDIUSBD12PW USB-Parallel Philips * "?3,000" "?5,630" "?4,287" "?2,700" PDIUSB12PW
2 FT245RL USB-UART FT야 * "?5,900" * "?6,900" "?5,000" FT245BL
3 CP2102 USB-UART SiLAB * "?3,800" "?4,500" "?6,160" "?2,350" CP2012-GM
4 PL2303X USB-UART * "?2,800" "?3,900" ?0 "?2,350" PL2303X
5 AT45DB011D-SSH-B 1Mb SPI Flash Atmel * "?1,800" "?1,600" "?1,331" "?1,200" AT45DB011D-SSH-B
6 AT45DB021D-SSH-B 2Mb SPI Flash Atmel * * * "?1,671" "?1,500" AT45DB021D-SSH-B
5 AT45DB041D-SSH-B 4Mb SPI Flash Atmel * * * "?1,996" "?1,880" AT45DB041D-SSU
6 AT45DB081D-SSH-B 8Mb SPI Flash Atmel * * * "?2,492" "?2,250" AT45DB081D-SSU
17 M25P10-AVMN6TP 1Mb SPI Flash ST * * ?830 * "?1,400" M25P10-AVMN6
18 M25P20-VMN6T 2Mb SPI Flash ST * * "?1,900" * "?1,500" M25P20-VMN6
7 LM1117S-ADJ LDO * ?250 ?300 * ?130 AME1117
7 LM1117S-2.5 LDO * ?250 ?300 * ?130 AME1117
7 LM1117S-3.3 LDO * ?250 ?300 * ?130 AME1117
8 K6R1016V1D-UC10 64k*16b SRAM SEC * "?1,360" "?5,160" *
9 K4S641632H-UC75 64Mb SDRAM SEC * "?3,500" "?1,320" *
9 K4S281632I-UC75 128Mb SDRAM SEC * * "?1,330" *
10 AT49F001-70TC 1Mb Flash Atmel * ?600 * *
11 AT49F002T-12JC 2Mb Flash Atmel * ?0 "?1,130" *
12 X-TAL * ?400 ?160 ?260
13 OSC Half Type OSC * "?1,250" "?1,200" "?1,200"
14 XC3S100E-TQG144 FPGA Xilinx * "?15,000" "?10,000" "?17,179"
15 XC3S200 FPGA Xilinx * "?24,000" "?24,320" ?0
16 XC3S250E-TQG144 FPGA Xilinx * * * "?23,679"
16 XC3S250E-TQG208 FPGA Xilinx * ?0 "?24,560" *
16 XC3S250E-FBG256 FPGA Xilinx * ?0 "?27,130" *
19 Header Box Male 2.54mm 2x5 * ?150 * *
20 Header Box Male 2.54mm 2x20 * ?480 * *
21 Header Box Female 2.54mm 2x5 * ?100 * *
22 Header Box Female 2.54mm 2x20 * ?170 * *
23 Header Box Female 2.54mm 2x20R * ?360 * *
19 Header Male 2.00mm 2x80 ?720 * * *
21 Header Female 2.00mm 2x80 "?1,620" * * *
24 PCI Connector * "?1,150" * *
25 Round Socket 2x4 * ?120 * *
26 PS2 Connector * ?400 * *
27 USB Connector A Type * ?310 * *
28 USB Connector B Type * ?330 * *
29 DVI * ?600 * *
30 TSB41AB2 IEEE1394 PHY TI * "?3,500" * *
31 LTDC-TX12P03 오디오 광출력 * * * "?1,238"
32 GPIFA352TZ0F 오디오 광출력 Sharp * * * "?1,826"
33 LCD Character CHAR 16x2 * "?10,500" "?7,000" *
34 LCD Graphic DOT 128x64 * "?10,800" "?9,000" *
35 LCD Color Graphic COLOR 128x160 * * "?12,000" *
36 LED SMD * * ?30 *
37 TR Switching SP8K22 ROHM ?0 ?0 ?0 ?0

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2022.02.13

0. 이전 작업

Full-HD에서 픽셀 노이즈 문제 있었음

 

1. 구글 검색후 찾은 내용

https://github.com/dpaul24/hdmi_pass_through_ZyboZ7-10?_ga=2.109261708.849719984.1644672110-464492581.1644672110 

 

GitHub - dpaul24/hdmi_pass_through_ZyboZ7-10: This is a simple design example showing how a HDMI signal can be passed through a

This is a simple design example showing how a HDMI signal can be passed through a FPGA without any type of processing on it. The Digilent Zybo Z7-10 development board has been used. - GitHub - dpau...

github.com

2. 새로운 프로젝트 생성

IP library에 문서 참조

* RX Ref Clock = 200MHz

* DDC 용 Data 파일도 포함되어 있음

 

3. Pin Assignment 문제

Elab, Syn, Impl 단계에서 Schematic 을 열면 I/O 선택 가능

xdc의 port 이름이 다르면 설정이 반영안됨

Degilent의 Master xdc를 다시 참고

##Clock signal
set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { sysclk }]; #IO_L12P_T1_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];


##Switches
set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L19N_T3_VREF_35 Sch=sw[0]
#set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L24P_T3_34 Sch=sw[1]
#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { sw[2] }]; #IO_L4N_T0_34 Sch=sw[2]
#set_property -dict { PACKAGE_PIN T16   IOSTANDARD LVCMOS33 } [get_ports { sw[3] }]; #IO_L9P_T1_DQS_34 Sch=sw[3]

#System Reset
set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { async_reset }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
set_false_path -from [get_ports async_reset]

##Buttons
#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { btn[0] }]; #IO_L12N_T1_MRCC_35 Sch=btn[0]
#set_property -dict { PACKAGE_PIN P16   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L24N_T3_34 Sch=btn[1]
#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { btn[2] }]; #IO_L10P_T1_AD11P_35 Sch=btn[2]
#set_property -dict { PACKAGE_PIN Y16   IOSTANDARD LVCMOS33 } [get_ports { btn[3] }]; #IO_L7P_T1_34 Sch=btn[3]


##LEDs
set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { LD0 }]; #IO_L23P_T3_35 Sch=led[0]
#set_property -dict { PACKAGE_PIN M14   IOSTANDARD LVCMOS33 } [get_ports { led[0] }]; #IO_L23P_T3_35 Sch=led[0]
#set_property -dict { PACKAGE_PIN M15   IOSTANDARD LVCMOS33 } [get_ports { led[1] }]; #IO_L23N_T3_35 Sch=led[1]
#set_property -dict { PACKAGE_PIN G14   IOSTANDARD LVCMOS33 } [get_ports { led[2] }]; #IO_0_35 Sch=led[2]
#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { led[3] }]; #IO_L3N_T0_DQS_AD1N_35 Sch=led[3]


##RGB LED 5 (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN Y11   IOSTANDARD LVCMOS33 } [get_ports { led5_r }]; #IO_L18N_T2_13 Sch=led5_r
#set_property -dict { PACKAGE_PIN T5    IOSTANDARD LVCMOS33 } [get_ports { led5_g }]; #IO_L19P_T3_13 Sch=led5_g
#set_property -dict { PACKAGE_PIN Y12   IOSTANDARD LVCMOS33 } [get_ports { led5_b }]; #IO_L20P_T3_13 Sch=led5_b

##RGB LED 6
#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { led6_r }]; #IO_L18P_T2_34 Sch=led6_r
#set_property -dict { PACKAGE_PIN F17   IOSTANDARD LVCMOS33 } [get_ports { led6_g }]; #IO_L6N_T0_VREF_35 Sch=led6_g
#set_property -dict { PACKAGE_PIN M17   IOSTANDARD LVCMOS33 } [get_ports { led6_b }]; #IO_L8P_T1_AD10P_35 Sch=led6_b

#HDMI RX
set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_scl_io }]; #IO_L22P_T3_34 Sch=hdmi_rx_scl
set_property -dict { PACKAGE_PIN Y19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_ddc_sda_io }]; #IO_L17N_T2_34 Sch=hdmi_rx_sda

set_property -dict { PACKAGE_PIN U19   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_clk_n }]; #IO_L12N_T1_MRCC_34 Sch=hdmi_rx_clk_n
set_property -dict { PACKAGE_PIN U18   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_clk_p }]; #IO_L12P_T1_MRCC_34 Sch=hdmi_rx_clk_p
set_property -dict { PACKAGE_PIN W20   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_data_n[0] }]; #IO_L16N_T2_34 Sch=hdmi_rx_n[0]
set_property -dict { PACKAGE_PIN V20   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_data_p[0] }]; #IO_L16P_T2_34 Sch=hdmi_rx_p[0]
set_property -dict { PACKAGE_PIN U20   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_data_n[1] }]; #IO_L15N_T2_DQS_34 Sch=hdmi_rx_n[1]
set_property -dict { PACKAGE_PIN T20   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_data_p[1] }]; #IO_L15P_T2_DQS_34 Sch=hdmi_rx_p[1]
set_property -dict { PACKAGE_PIN P20   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_data_n[2] }]; #IO_L14N_T2_SRCC_34 Sch=hdmi_rx_n[2]
set_property -dict { PACKAGE_PIN N20   IOSTANDARD TMDS_33   } [get_ports { hdmi_in_data_p[2] }]; #IO_L14P_T2_SRCC_34 Sch=hdmi_rx_p[2]

set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { hdmi_in_hpd }]; #IO_L22N_T3_34 Sch=hdmi_rx_hpd


##HDMI RX CEC (Zybo Z7-20 only)
#set_property -dict { PACKAGE_PIN Y8    IOSTANDARD LVCMOS33 } [get_ports { hdmi_rx_cec }]; #IO_L14N_T2_SRCC_13 Sch=hdmi_rx_cec


#HDMI TX
#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { hdmi_out_ddc_scl_io }]; #IO_L16P_T2_35 Sch=hdmi_tx_scl
#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { hdmi_out_ddc_sda_io }]; #IO_L16N_T2_35 Sch=hdmi_tx_sda

set_property -dict { PACKAGE_PIN H17   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_clk_n }]; #IO_L13N_T2_MRCC_35 Sch=hdmi_tx_clk_n
set_property -dict { PACKAGE_PIN H16   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_clk_p }]; #IO_L13P_T2_MRCC_35 Sch=hdmi_tx_clk_p
set_property -dict { PACKAGE_PIN D20   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[0]  }]; #IO_L4N_T0_35 Sch=hdmi_tx_n[0]
set_property -dict { PACKAGE_PIN D19   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[0]  }]; #IO_L4P_T0_35 Sch=hdmi_tx_p[0]
set_property -dict { PACKAGE_PIN B20   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[1]  }]; #IO_L1N_T0_AD0N_35 Sch=hdmi_tx_n[1]
set_property -dict { PACKAGE_PIN C20   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[1]  }]; #IO_L1P_T0_AD0P_35 Sch=hdmi_tx_p[1]
set_property -dict { PACKAGE_PIN A20   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_n[2]  }]; #IO_L2N_T0_AD8N_35 Sch=hdmi_tx_n[2]
set_property -dict { PACKAGE_PIN B19   IOSTANDARD TMDS_33  } [get_ports { hdmi_out_data_p[2]  }]; #IO_L2P_T0_AD8P_35 Sch=hdmi_tx_p[2]

Board 정보를 가지고 hdmi_in_hpd를 사용하면 Vector가 됨

=> hdmi_in_hpd[0]로 바꿀 것

 

Impl Error

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets design_1_i/clk_wiz_0/inst/clk_in1_design_1_clk_wiz_0_0] > design_1_i/clk_wiz_0/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X1Y126 design_1_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0 The above error could possibly be related to other connected instances. Following is a list of all the related clock rules and their respective instances. Clock Rule: rule_mmcm_bufg Status: PASS Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device design_1_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0 and design_1_i/clk_wiz_0/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

=> Clock Wizard에서 MMCM -> PLL로 변경 => impl OK

화면 출력 안됨

PLL lock 신호는 모두 정상 (LED로 출력)

Impl Schematic에서 hdmi_in_data_p/n이 Open 되어 있음???

=> dvi2rgb의 pRst를 low active로 바꾸고 "0"으로 고정하였기 때문에 data channel을 무시한 것 같음

"1"로 바꾸고 정상동작

노이즈 문제가 있었던 기존 프로젝트는 hdmi_in_clk에 대한 constraint를 추가하여 해결

create_clock -period 6.25 -waveform {0.000 3.125} [get_ports hdmi_in_clk_p]

* xdc에 port name 조심

* instance의 port 값을 고정할 때 polarity조심

* 내부 clock에 대한 constraint 지정할 것

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0. Ref

https://elixir.bootlin.com/linux/latest/source/drivers/media/i2c/ov5647.c

https://github.com/torvalds/linux/blob/master/drivers/media/i2c/ov5647.c

 

GitHub - torvalds/linux: Linux kernel source tree

Linux kernel source tree. Contribute to torvalds/linux development by creating an account on GitHub.

github.com

1. 차이점

7.2 SCCB control [0x3100 ~ 0x3108]

  OV5640 OV5647
0x3100 SCCB ID 0x78 0x6C
0x300A CHIP ID HIGH BYTE 0x56 0x56
0x300B CHIP ID LOW BYTE 0x40 0x47
0x3103 SCCB SYSTEM CTRL1(Debug??) 0x11 ???
0x3008 SYSTEM CTROL0 (reset) 0x82 ???
0x0100 SW Standby   0x01
0x0103 SW Reset   0x01

address를 0x78 -> 0x6C로 바꾸고 init 함수에서 register 설정값을 OV5647 1080p 30 10bit로 변경하였으나

화면 깨짐

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[FPGA] ZYBO Z7: UART @PS  (0) 2022.02.12
[FPGA] ZYBO Z7: UART with Pmod IPs  (0) 2022.02.12

0. Ref

https://rubber-tree.tistory.com/75?category=954288 

 

[Zybo z7-20 보드 실습] Pcam 5C 영상 출력 (MIPI - HDMI)

프로젝트 컨셉 이번에는 Zybo z7-20 보드로 해보고 싶었던 카메라 Pcam 5C 실습을 해보겠습니다 PCam 5C는 MIPI 통신을 사용하며 보드에 장착되어 있는 HDMI TX 포트를 이용하여 모니터에 촬영되는 영상을

rubber-tree.tistory.com

 

https://digilent.com/reference/learn/programmable-logic/tutorials/zybo-z7-pcam-5c-demo/start?_ga=2.155411774.408121669.1620950911-477770147.1617751612 

 

Zybo Z7 Pcam 5C Demo - Digilent Reference

 

digilent.com

https://github.com/Digilent/Zybo-Z7-20-pcam-5c/releases

 

Releases · Digilent/Zybo-Z7-20-pcam-5c

Contribute to Digilent/Zybo-Z7-20-pcam-5c development by creating an account on GitHub.

github.com

 


1. 다운로드

Github에서 최신 다운로드

* Source가 아닌 전체 다운로드, README.md에 자세한 설명

 

2. Vivado (2021.1)

*.xpr로 프로젝트 열기

bitstream을 생성하지 않고 바로 export

 

3. Vitis

xsa를 가지고 프로젝트 생성

empty -> import source -> sdk가 있는 디렉토리 지정

buitl -> xparamters.h 없다고 에러


4. 재검색

Vivado -> Vitis

https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi

 

Getting Started with Vivado and Vitis for Baremetal Software Projects - Digilent Reference

 

digilent.com

xparameters.h는 Vivido 에서 export할 때 생성됨??

xparameters.h  is a file generated during the process of exporting a platform from Vivado

=> Vitis Include path에 Vavado wrapper processor include 디렉코리 위치 추가

 

=> 우선 Application이 아닌 Platform을 먼저 빌드해야 할 것 같음, 하지만 에러

"Compiling MIPI_CSI_2_RX..." arm-xilinx-eabi-gcc.exe: error: *.c: Invalid argument arm-xilinx-eabi-gcc.exe: fatal error: no input files compilation terminated. make[3]: *** [Makefile:18: libs] Error 1 make[2]: *** [Makefile:46: ps7_cortexa9_0/libsrc/MIPI_CSI_2_RX_v1_0/src/make.libs] Error 2 make[1]: *** [Makefile:18: all] Error 2

구글에서 "Vitis MIP_CSI_2_RX error" 검색 결과

https://rightxlight.co.jp/achievements/zybo-z7-pcam-5c-demo%E3%82%92vivado-2020-02%E3%81%A7%E5%8B%95%E4%BD%9C%E3%81%95%E3%81%9B%E3%81%A6%E3%81%BF%E3%81%9F/

 

 

Zybo Z7 Pcam 5C DemoをVivado 2020.02で動作させてみた

とある業務の動作検証として、Zybo Z7 Pcam 5C DemoをVivado 2020.02で実行したのですが、推奨バージョンの違いから何点か詰ま

rightxlight.co.jp

 

6개 Makefile 수정

#OUTS = *.o
OUTS = $(addsuffix .o, $(basename $(wildcard *.c)))

=> 에러 => Vitisa 내에서 수정 => 에러


https://qiita.com/kan573/items/b095f9e93eb48bcf3874

 

1500円ZYNQ基板とPiCamV2でZyboのPcam5Cデモを動かす(前編) - Qiita

(2021.5.21 更新) 8-2. Digilent 製 IP のアップグレード の項目を追加しました。 これをやらないと、エクスポートした .xsa に含まれるドライバの makefile が古い物になり、プロットフォームプロジ...

qiita.com

Digilent Vivado IP 다운로드후

Zybo-Z7-20-pcam-5c-2019.1\vivado_proj\Zybo-Z7-20-pcam-5c.ipdefs\repo_0\vivado-library\ip 복사

(직접 다운 받은 버젼의 Makefile은 OBJECTS=... 로 변경되어 있음 @2022/02/12)

 

=> 직접 복사하면 Managing Output Products 에서 끝나지 않음


VPG에서 문제가 있는 것 같음

https://support.xilinx.com/s/question/0D52E00006hpYEVSA2/vivado-20202-generate-block-design-does-not-become-finish?language=en_US 

 

Vivado 2020.2 => Generate Block Design does not become finish

 

support.xilinx.com

우선 빌드에서 문제가 잇는 MIPI_D_PHY, MIPI_CSI의 Makefile만 수정 -> Generate Output Product (중간에 Cancel) -> Export -> Vitis -> Makefile이 수정이 안되어 있음

 

Vivado IP library에서 Makefile의 내용 전체를 Vitis에서 직접 붙여넣기 해서 정상 적으로 빌드.

* 프로젝트의 센서 (OV5640)와 Raspberry Pi 용 센서가 달라 Error 발생

Connected to COM5 at 115200
terminate called after throwing an instance of 'digilent::OV5640::HardwareError'
  what():  Got 00 1a. Expected 56 40

OV5640.h를 수정하여 Sensor ID확인을 막음

	void init()
	{
		uint8_t id_h, id_l;
		readReg(reg_ID_h, id_h);
		readReg(reg_ID_l, id_l);
		if (0) //(id_h != dev_ID_h_ || id_l != dev_ID_l_)

화면은 깨지지만 일단 출력됨

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0. Ref

https://rubber-tree.tistory.com/60?category=954288 

 

[Zybo z7-20 보드 실습] ARM 프로세스 활용하기 - PS

Xilinx에서 제공하는 FPGA 칩 종류 이 중 ARM processor를 갖고 있는 FPGA 칩은 ZYNQ 뿐이다. ARM 프로세스가 구현되어 있는 FPGA의 ZYNQ 보드를 활용하기 위한 실습이다. ZYNQ의 2가지 영역 Processing System (..

rubber-tree.tistory.com

 

1. Viviado

Project -> Create Block Design -> Add ZYNQ7 -> Double Click ->

MIO Configuration: UART 만

PS-PL : AXI 끄기

Clock : Clock 끄기

Run Block Automation -> Validation -> Create HDL Wrapper

Generate Bitstream -> Export Hardware Platform(include Bitstream)

(Tools) Launch Vitis -> ... -> Create Project form XSA

 

Hello World Template으로 코드 생성하면

Printf -> ps7_uart로 전송!? (115200)

 

Vitis Serial Terminal  -> Xilinx Program Device -> Run as Launch On Hardware

** Run As (none applicable)

 

Explorer -> Hello_World -> Run As

자동으로 bitstream을 다운로드하고 실행됨

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