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[FPGA] IP-XACT 생성

2025.12.18IP-XACT 생성 방버1. Kactus22. Vivado IP packager3.Kactus2https://github.com/kactus2/kactus2dev GitHub - kactus2/kactus2dev: Kactus2 is a graphical EDA tool based on the IP-XACT standard.Kactus2 is a graphical EDA tool based on the IP-XACT standard. - kactus2/kactus2devgithub.comhttps://sourceforge.net/projects/kactus2/files/Kactus2SetupWin64bit3.13.5.exe/download IP Packager# Vivado 실행 시 ..
IT/FPGA 2025. 12. 18. 01:16
[FPGA] Vivado Programmer @MacBook (Arm)

2025.03.24검색: vivado programmer macoshttps://forum.digilent.com/topic/20046-programming-fpga-boards-from-a-mac/https://github.com/byu-cpe/BYU-Computing-Tutorials/wiki/Program-7-Series-FPGA-from-a-Mac-or-Linux-Without-Xilinx Program 7 Series FPGA from a Mac or Linux Without XilinxCollection of tutorials from the BYU Computer Engineering Group - byu-cpe/BYU-Computing-Tutorialsgithub.com맥북에 설치homeb..
IT/FPGA 2025. 3. 24. 15:46
[FPGA] ZCU102: PL Clock, Reset 설정

2025.03.13ZYBO Z7과는 다르게 PL용 Single-ended Clock이 없는 것 같다.ZYBO용 PL LED를 돌리면 동작하지 않는다.클럭 설정을 하여 확인한 결과PL 용 clock은 clk_74_25, clk_125 같음 clk_74_25 bank44clk_125 bank47Copilot을 통해 diff2single code 확인module differential_to_single_ended ( input wire clk_p, // Differential clock positive input wire clk_n, // Differential clock negative output wire clk_out // Single-ended clock output); wir..
IT/FPGA 2025. 3. 13. 16:01
[FPGA] ZCU102: VPG-HDMI

2025.03.13ZYBO에서 진행했던 VPG를 ZCU102에서 구현하려고 하는데,rgb2dvi 가 안보인다.https://github.com/Digilent/vivado-library링크에서 다시 다운받고플로우 네비게이터 -> 프로젝트 관리자 -> 설정, IP -> 리포지토리 추가IP 리스트에 다른 것들은 나오는데 rgb2dvi 안나온다.버전에 제한이 걸렸나 싶어 2022.1, 2024.2 둘다 안된다.Digilent 제품에만 제한이 걸린 것인가 검색https://forum.digilent.com/topic/24942-ipcore-rgb2dvi-for-zynq-ultrascale/ 답변내용Unfortunately, this IP (rgb2dvi) is not supported for Ultrascale..
IT/FPGA 2025. 3. 13. 14:19
[FPGA] ZYBO Z7: VPG

2025.03.12## This file is a general .xdc for the Zybo Z7 Rev. B## It is compatible with the Zybo Z7-20 and Zybo Z7-10## To use it in a project:## - uncomment the lines corresponding to used pins## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project##Clock signalset_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { sys..
IT/FPGA 2025. 3. 12. 18:59
[FPGA] ZYNQ Mini 정보, Vivado 2024.2

205.02.02https://onedrive.live.com/?authkey=%21AOgFjM4waJnTONY&id=B2CDC3A30980D5BD%21182971&cid=B2CDC3A30980D5BD Microsoft OneDrive onedrive.live.com 기본+5V MustMain Power: Type-C@JTAGBoot ModeUU(00): JTAGDU(10): QSPI, from FLASH, OLED Demo, Heat!!!DD(11): SD Card, petalinuxPetalinuxmicroSD, FAT3202 Routine Project > "LINUX part \01petalinux2018.3 run \compiled boot  file"BOOT.BIN, image.ubUART p..
IT/FPGA 2025. 2. 2. 20:31
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