[FPGA] ZCU102: PL Clock, Reset 설정

2025.03.13

ZYBO Z7과는 다르게 PL용 Single-ended Clock이 없는 것 같다.

ZYBO용 PL LED를 돌리면 동작하지 않는다.

---

클럭 설정을 하여 확인한 결과

PL 용 clock은 clk_74_25, clk_125 같음

 

clk_74_25 bank44

clk_125 bank47

Copilot을 통해 diff2single code 확인

module differential_to_single_ended (
    input wire clk_p,  // Differential clock positive
    input wire clk_n,  // Differential clock negative
    output wire clk_out // Single-ended clock output
);

    wire clk_ibufds;

    // Instantiate the IBUFDS primitive
    IBUFDS #(
        .DIFF_TERM("FALSE"), // Differential Termination
        .IBUF_LOW_PWR("TRUE"), // Low power (TRUE) vs. performance (FALSE) setting for the I/O buffer
        .IOSTANDARD("DEFAULT") // Specify the input I/O standard
    ) IBUFDS_inst (
        .I(clk_p),  // Connect positive differential input
        .IB(clk_n), // Connect negative differential input
        .O(clk_ibufds) // Single-ended clock output
    );

    assign clk_out = clk_ibufds;

endmodule

module led_stream(
    output reg [3:0] led,  // LED4 to LED1, 1 on, 0 off
    input            clk_74_25_p,  // FPGA PL clock, 50 MHz
    input            clk_74_25_n,  // FPGA PL clock, 50 MHz
    input            rst // FPGA reset pin
);
 reg [31:0] cnt;
 reg [1:0]  led_on_number;
    //clock input 50000000
parameter CLOCK_FREQ  =50000000;
parameter COUNTER_MAX_CNT=CLOCK_FREQ/2-1;//change time 0.5s


   wire clk_74_25;

      // Instantiate the differential to single-ended converter
    differential_to_single_ended diff_to_single (
        .clk_p(clk_74_25_p),
        .clk_n(clk_74_25_n),
        .clk_out(clk_74_25)
    );

create_clock -period 13.468 -name clk_sys [get_ports clk_74_25_p]
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets clk_sys]

## Sys clock
set_property -dict {PACKAGE_PIN AK14 IOSTANDARD LVDS_25} [get_ports clk_74_25_n]
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25} [get_ports clk_74_25_p]
...
## LEDs
set_property -dict {PACKAGE_PIN AG14 IOSTANDARD LVCMOS33} [get_ports {led[3]}]
set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVCMOS33} [get_ports {led[2]}]
set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVCMOS33} [get_ports {led[1]}]
set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS33} [get_ports {led[0]}]

 

 

---

Reset 을 없애면 LED가 동작, 혹시나 싶어서 Polarity 확인

 

24 SW20 aUser I/O (CPU_RESET pushbutton switch, Active-High) E-Switch TL3301EP100QG 53
CPU Reset Pushbutton (Active‐High) AM13 CPU_RESET LVCMOS33 SW20.3

Active High 같다.

Verilog, xdc 수정

    always @(posedge clk_74_25, posedge rst) begin
        if(rst) begin
            cnt <= 32'd0;
            led_on_number <= 2'd0;
        end
        else begin
            cnt <= cnt + 1'b1;
            if(cnt == COUNTER_MAX_CNT) begin//����0.5s
                cnt <= 32'd0;
                led_on_number <= led_on_number + 1'b1;
            end
        end
    end

# reset
set_false_path -from [get_ports rst]
set_property -dict {PACKAGE_PIN AM13 IOSTANDARD LVCMOS33} [get_ports rst]

 

결론

• Clock
  
  • PL용 사용 clk_74_25, clk_125
  • diff2single 변환 필요
  • xdc에  LVDS_25 p/n
• Reset
  • CPU_RESET 사용
  • active-high

---

 추가로 125MHz 테스트

일단 이름은 그대로 두고 핀만 바꿔서 테스트

## Sys clock
set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVDS_25} [get_ports clk_74_25_n]
set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVDS_25} [get_ports clk_74_25_p]

clk_125 핀도 정상 동작