[FPGA] ZYBO Z7: UART (Pmod USBUART)

0. Ref

https://digilent.com/reference/pmod/pmodusbuart/start?redirect=1 

Pmod USBUART - Digilent Reference

Pmod Connector 연결하여 PL에서 사용가능

1. ZYBO Z7 Port

clock: K11 <- Ethernet Phy Clock 125MHz

Button SW[4] = {K18, P16, K19, Y16}

Slide SW[4] = {G15, P15, W13, T16}

LED[4] = {M14, M15, G14, G15}

 

Pmod Port

Pmod JA (XADC)	Pmod JB (Hi-Speed)	Pmod JC (Hi-Speed)	Pmod JD (Hi-Speed)	Pmod JE (Hi-Speed)	Pmod JF (MIO)
JA1: N15	JB1: T20	JC1: V15	JD1: T14	JE1: V12	JF1: MIO-13
JA2: L14	JB2: U20	JC2: W15	JD2: T15	JE2: W16	JF2: MIO-10
JA3: K16	JB3: V20	JC3: T11	JD3: P14	JE3: J15	JF3: MIO-11
JA4: K14	JB4: W20	JC4: T10	JD4: R14	JE4: H15	JF4: MIO-12
JA7: N16	JB7: Y18	JC7: W14	JD7: U14	JE7: V13	JF7: MIO-0
JA8: L15	JB8: Y19	JC8: Y14	JD8: U15	JE8: U17	JF8: MIO-9
JA9: J16	JB9: W18	JC9: T12	JD9: V17	JE9: T17	JF9: MIO-14
JA10: J14	JB10: W19	JC10: U12	JD10: V18	JE10: Y17	JF10: MIO-15

 

2. Vivado 순서

Board 파일을 이용하여 프로젝트 생성

Verilog 코드 추가 -> Open Elaborated Designs -> Schematic -> Pin Assign -> Generate Bitstream

또는

IP Integrator -> Create Block Design -> Code Drag&Drop -> Create Port -> Generate Output Products

 -> Generate HDL Wrapper -> Elaborated Designs ...

 

clk_wiz: 외부 125MHz 에서 내부 50MHz clock 생성

util_vector_logic: Pull-Down 되어 있는 Button SW 입력을 "1" 로 뒤집어 active low Reset에 연결

sw0,1: UART mode 설정

je1,2 : JE Connector에 Pmod USB UART와 연결

xslice: 8bit 중 LED로 갈 4bit 만 연결

 

3. PC와 연결

Hardware Manager에서 PL programming

Pmod USBUART와 PC를 USB Cable로 연결

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